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T-CREST

 

Time-predictable Multi-Core Architecture for Embedded Systems

Funding Programme

European Commission - FP7 ICT-2011-7

Coordinator

The Open Group (UK)

Partners

Technical University of Denmark (DK); AbsInt Angewandte Informatik (DE); Vienna University of Technology (AT), Eindhoven University of Technology (ND); University of York (UK); GMV (PT)

Start Date

September 2011

Duration

36 months

Description

Safety-critical systems are important parts of our daily life. Those systems are also called dependable systems, as our lives can depend on them. Examples are controllers in an airplane, breaking controller in a car, or a train control system. Those safety-critical systems need to be certified and the maximum execution time needs to be bounded and known so that response times can be assured when critical actions are needed. Note that just using a faster processor is not a solution for time predictability.

Standard computer architecture is driven by the following paradigm: make the common case fast and the uncommon case correct. This design approach leads to architectures where the average-case execution time is optimized at the expense of the worst-case execution time (WCET). Modelling the dynamic features of current processors, memories, and interconnects for WCET analysis often results in computationally infeasible problems. The bounds calculated by the analysis are thus overly conservative.

Within the project we will propose novel solutions for time-predictable multi-core and many-core system architectures. The resulting time-predictable resources (processor, interconnect, memories, etc.) will be a good target for WCET analysis and the WCET performance will be outstanding compared to current processors. Time-predictable caching and time-predictable chip-multiprocessing (CMP) will provide a solution for the need of more processing power in the real-time domain.

Next to the hardware (processor, interconnect, memories), a compiler infrastructure will be developed in the project. WCET aware optimization methods will be developed along with detailed timing models such that the compiler benefits from the known behaviour of the hardware. The WCET analysis tool aiT will be adapted to support the developed hardware and guide the compilation.

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